The present invention relates to a logic circuit which generates pulse sequences of different phases.
Technologies for digitizing an analog signal to facilitate signal processing or to process the digital signal by a computer have made remarkable progress by recent semiconductor technology, particularly LSI technology. Among others, an analog-to-digital converter (A/D converter) which serves as an interface of the analog signal and the digital signal has changed from a module type or hybrid type to a faster and more accurate monolithic IC. A successive-approximation type monolithic A/D converter has been vigorously developed.
As shown in FIG. 1, the successive-approximation type A/D converter comprises an input span resistor (R.sub.i) 101, a comparator 102, shift counters 103 (103a-104d) and current-steering switches 105 (105a-105d) including binary weighted current sources. The shift counters 103 and the memories 104 constitute a successive approximation resistor (SAR). A sampling and hold signal V.sub.i is applied to an input terminal 106, a reference voltage V.sub.s is applied to a terminal 107, and a clock pulse and a reset pulse are applied to a terminal 108 and a terminal 109, respectively. Numeral 110 denotes an output line of the comparator 102, numeral 111 denotes an output current summing line and numeral 112 denotes digital output lines of the memory 104.
In the operation of the comparator, shift pulses are sequentially applied from the shift counters 103a, 103b, 103d to the memories 104a, 104b, . . . 104d so that the current-steering switches 105a, 105b, . . . 105d having weights of 1/2.sup.1, 1/2.sup.2, . . . 1/2.sup.n, respectively, are sequentially turned on. The output pulse of the counter 103a is first applied to the memory 104a to turn on the switch 105a to supply a current I.sub.o to the summing line 111 and the comparator 102 compares (V.sub.i -R.sub.i I.sub.o) with V.sub.s. If (V.sub.i -R.sub.i I.sub.o)&gt;V.sub.s, "1" is stored in the memory 104a. Then, the output pulse of the counter 103b is applied to turn on the switch 105b to supply a current I.sub.o /2 to the summing line 111. The switch 105a is also turned on by the content (stored "1") of the memory 104a to supply the current I.sub.o to the summing line 111. As a result, a total current of (I.sub.o +I.sub.o /2) is supplied to the summing line 111. The comparator 102 compares Vi-(I.sub.o +I.sub.o /2)R.sub.i with V.sub.s and stores the compare result in the memory 104b. Similarly, the compare results of the comparator 102 are stored in the memories 104c, . . . 104d to produce the digital output 112.
The SAR comprising the shift counters 103 and the memories 104 used in the successive approximation type A/D converter may be constructed as shown below.
FIG. 2 shows an example of the SAR which comprises D-type flip-flop (D-type F-F).
In FIG. 2, like numerals to those shown in FIG. 1 denote like elements, and numerals 1030, 103a, . . . 103d and 104a . . . 104d denote D-type F-F's Each of the D-type F-F's comprises six NAND gates. FIG. 3 shows waveforms at various points in FIG. 2 and the numerals corresponding to those in FIG. 2 denote the corresponding output waveforms. In the illustrated example, the D-type F-F's are triggered by trailing edges. The operation is explained below. When the reset pulse 109 is applied, the D-type F-F 1030 is set while all other D-type F-F's are reset. Accordingly, under this condition a Q-output of the D-type F-F 1030 assumes an "H" level. At a trailing edge of the next clock pulse 108, the D-type F-F 103a reads in the "H" level at its D-input. At a trailing edge of the next sequential clock pulse, the D-input of the D-type F-F 103a is "L" and hence a Q-output thereof is "L". On the other hand, the D-type F-F 103b assumes the "H" level. In a similar manner, shift pulse sequences as shown by 103a, 103b, . . . 103d in FIG. 3 are produced.
On the other hand, the memories 104a, 104b, . . . 104d are clocked by the corresponding shift pulses. Consequently, the D-type F-F 104a reads in its D-input which is "H" or "L" level of the comparator output 110 at the trailing edge of the output of the D-type F-F 103a so that the D-type F-F's 104a . . . 104d produce Q-outputs as shown by 104a . . . 104d in FIG. 3. Hatched areas show conditions responding to the output of the comparator 102. The current-steering switches are driven by wired-OR signals of Q-outputs of the memory D-type F-F's 104a . . . 104d and Q-outputs of the shift counter D-type F-F's 103a . . . 103d, that is, signals 105a, 105b, 105c and 105d.
A defect of the SAR comprising a D-type F-F is an operational delay in the D-type F-F's as shown in FIG. 3. At the trailing edge of the D-type F-F 103a, the D-type F-F 104a is triggered, but a gate delay occurs because the D-type F-F usually comprises a plurality of NAND gates. Consequently, a time delay t.sub.PM occurs before the D-type F-F 104a produces the Q-output in response to the trailing edge of the D-type F-F 103a. Similar time delays occur between the clock pulse 108 and the output shift pulse sequencies of the D-type F-F's 103a . . . 103d. Relative time delay thereof is represented by t.sub.PD. If the output of the comparator is "L" no time delay t.sub.PM occurs between the shift pulse and the memory output, but if the output of the comparator is "H", the time delay or gap t.sub.PM significantly deteriorates the accuracy. If the gap occurs for the most significant bit (MSB), the current-steering switch is turned off when the shift pulse changes from " L" to "H" as shown by 105a to 105d of FIG. 3. Thereafter, the current-steering switch corresponding to the second bit is turned on by the shift pulse corresponding to the second bit. When the MSB memory assumes the "L" level after the time delay t.sub.PM, the current-steering switch corresponding to the MSB is again turned on. Thus, the current of the highest weight varies significantly in a very short time period. This is called glitch which causes ringing in an analog circuit and causes a longer settling time and a conversion error.
A second defect is a large number of gates required in the SAR. This is disadvantageous in the design of the monolithic IC in view of chip size and power dissipation.
On the other hand, instead of the D-type F-F arrangement shown in FIGS. 2 and 3, the shift counter of the SAR may be constructed by a synchronous counter and AND gates as shown in FIG. 4, in which numerals 401 and 402 denote T-type F-F's and numerals 403 to 407 denote AND gates. The like numerals to those in FIG. 1 denote the like elements. Symbols A, A of 401 and B, B of 402 denote outputs of different phases, respectively.
FIG. 5 shows a time chart for the shift pulse sequence generating circuit shown in FIG. 4. The numerals corresponding to those shown in FIG. 4 denote the corresponding output waveforms.
In the example shown in FIG. 4, as is apparent from FIG. 5, the width of each of the shift pulses is equal to a period T of the clock pulse as a result of the use of the synchronous counter. However, the pulse interval of the shift pulse sequence is not always an integer multiple of T and hence errors occur in the gate delay times t.sub.g of the T-type F-F's 401 and 402, where t.sub.g is a delay time per gate of the NAND gates of the T-type F-F's 401 and 402 (to be explained with reference to FIG. 6) and the AND gates 403 to 407. In a system which operates in synchronism with time T, for example, an A/D converter, the fluctuation in time of the shift pulse sequence due to the gate delay time t.sub.g is a kind of noise and causes a jitter distortion.
In the construction shown in FIG. 4, the T-type F-F comprises NAND gates 601, a resistor 602 and a capacitor 603, as shown in FIG. 6. It is similar to an Eccles-Jordan flip-flip. A clock pulse is applied to a terminal T and a set pulse and a reset pulse are applied to terminals S and R, respectively. However, the T-type F.F blocks the realization of a high integration density IC because it uses R-C elements. Accordingly, a master-slave type J-K F-F which has more general applications is frequently used.
FIG. 7 shows a basic circuit of the master-slave type J-K F-F. In FIG. 7, numeral 701 denotes NAND gates and numeral 702 denotes AND gates. In order to use the J-K F-F as the T-type F-F, a J-K terminal is kept at the "H" level and a clock pulse is applied to a terminal C.sub.p. However, since the J-K F-F requires eight gates per pulse, it blocks the IC implementation.
As described thus far, a logic circuit which is fully satisfactory to the monolithic IC implementation of the SAR for the high speed and high accuracy sequential approximation type A/D converter has not been provided.